The present invention generally relates to the field of semiconductor memories. More particularly, the present invention relates to a DRAM and a memory core utilizable in embedded memories including DRAMs (dynamic random access memories) and logical circuits.
The level of integration of memories, particularly the level of DRAM integration, has been improved increasingly year by year. In order to avoid a reduction of the serviceable time of memories, a longer refresh cycle period is required. The level of real performance values required for data retention times becomes higher. It seems hard for process devices to meet such requirements.
Referring now to FIG. 23, the value of real performance of the memory data retention time will be described.
FIG. 23 outlines a conventional DRAM. Cs is a storage capacitor in a DRAM memory cell. WL1 and WL2 are word lines. bit is a bit line and xbit is a bit line in complementary relationship with the bit line bit. Vpre is a bit line precharge voltage. Ppre is a precharge control line. SA is a sense amplifier.
The operation of the DRAM is briefly explained. The precharge control line Ppre first enters the high level state and the bit lines bit and xbit are set at the precharge level Vpre. Subsequently, the precharge control line Ppre enters the low level state. This is followed by an increase in the potential of the word line WL1 and a micropotential is produced by a signal charge, stored in the memory cell storage capacitor Cs, in the bit line bit. This micropotential produced is subjected to amplification processing in the sense amplifier SA.
If a potential just before the word line WL1 undergoes an increase in potential, stored in the memory cell storage capacitor Cs, is Vcs, then a conservation of charge before and after a cell transistor conducts can be written by: EQU Cs(Vcs-Vplate)+Vpre*CB=Cs(Vr'-Vplate)+Vr'*CB
where Vplate is the cell plate potential, CB is the capacitance of the bit lines bit and xbit, and Vr' is the bit line potential determined after an electric charge is read out from the memory cell.
From this equation, a microvoltage Delta -V to be amplified in the sense amplifier SA is expressed by: EQU Delta-V=Vr'-Vpre=a*(Vcs-Vpre) a=Cs/(Cs+CB)
Only when the microvoltage Delta -V exceeds the sensitivity limit of the sense amplifier SA (+-Vsa), data are read out correctly. For example, if a "1" is written and is then read out, this produces a voltage expressed by: EQU Delta-V=a*(Vdd-Vpre)=0.2*(3.3-1.65)=330 mV
where Vdd is the supply voltage. On the other hand, if a "0" is written and is then read out, this produces a potential that may be expressed by: EQU Delta-V=a*(0-Vpre)=0.2*(-1.65)=-330 mV
Here, a=0.2, Vdd=3.3 V, and Vpre=Vdd/2.
Usually, the sense amplifier's sensitivity limit Vsa is about 50 mV. The DRAM operates normally without problems.
Next, consider a case in which there occurs a leakage current from the memory cell storage capacitor Cs therefore producing a difference between a voltage written to Cs and a voltage read out from Cs. For instance, suppose here a case of writing a "1", wherein a malfunction occurs at the time when the level of voltage reduces down to VcslL. It follows from a*(VcslL-Vpre)=Vsa that 0.2*(VcslL-1.65)=0.05. This shows that the malfunction starts occurring when VcslL=1.9 V. A length of time up to the time such a limit is reached is a real performance value of the data retention time. This relationship is illustrated by reference to FIG. 24.